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data sheet ?2009 cadeka microcircuits llc www.cadeka.com c omlinear clc1011, clc2011, clc4011 low power, low cost, rail-to-rail i/o amplifers rev 1a c omlinear ? clc1011, clc2011, clc4011 low power, low cost, rail-to-rail i/o amplifers f e a t u r e s n 136a supply current n 4.9mhz bandwidth n output swings to within 20mv of either rail n input voltage range exceeds the rail by >250mv n 5.3v/s slew rate n 21nv/hz input voltage noise n 16ma output current n fully specifed at 2.7v and 5v supplies n clc1011: pb-free sot23-5, sc70-5, soic-8 n clc2011: pb-free soic-8, msop-8 n clc4011: pb-free soic-14. tssop-14 a p p l i c a t i o n s n portable/battery-powered applications n pcmcia, usb n mobile communications, cell phones, pagers n adc buffer n active flters n portable test instruments n notebooks and pdas n signal conditioning n medical equipment n portable medical instrumentation general description the comlinear clc1011 (single), clc2011 (dual), and clc4011 (quad) are ultra-low cost, low power, voltage feedback amplifers. at 2.7v, the clcx011 family uses only 136a of supply current per amplifer and are designed to operate from a supply range of 2.5v to 5.5v (1.25 to 2.75). the input voltage range exceeds the negative and positive rails. the clcx011 family of amplifers offer high bipolar performance at a low cmos prices. they offer superior dynamic performance with 4.9mhz small signal bandwidths and 5.3v/s slew rates. the combination of low power, high bandwidth, and rail-to-rail performance make the clcx011 amplifers well suited for battery-powered communication/computing systems. typical performance examples ordering information part number package pb-free rohs compliant operating temperature range packaging method clc1011isc5x* sc70-5 yes yes -40c to +85c reel clc1011ist5x* sot23-5 yes yes -40c to +85c reel clc2011iso8x soic-8 yes yes -40c to +85c reel clc2011imp8x* msop-8 yes yes -40c to +85c reel CLC4011ISO14X* soic-14 yes yes -40c to +85c reel clc4011itp14x* tssop-14 yes yes -40c to +85c reel moisture sensitivity level for all parts is msl-1. *advance information - future products. magnitud e (1db/div) frequency (mhz) 0.01 0.1 1 10 v o = 4v pp v s = 5v v o = 1v pp v o = 2v pp outpu t voltag e (0.27v/div) input voltage (0.4v/div) -2.0 0 2.0 -1.35 0 1.35 r l = 10k? r l = 1k? r l = 75/100? r l = 200? r l = 100? r l = 75? large signal frequency response output swing vs. load a m p l i f y t h e h u m a n e x p e r i e n c e
data sheet c omlinear clc1011, clc2011, clc4011 low power, low cost, rail-to-rail i/o amplifers rev 1a ?2009 cadeka microcircuits llc www.cadeka.com 2 clc1011 pin assignments pin no. pin name description 1 out output 2 -v s negative supply 3 +in positive input 4 -in negative input 5 +v s positive supply clc2011 pin confguration pin no. pin name description 1 out1 output, channel 1 2 -in1 negative input, channel 1 3 +in1 positive input, channel 1 4 -v s negative supply 5 +in2 positive input, channel 2 6 -in2 negative input, channel 2 7 out2 output, channel 2 8 +v s positive supply clc4011 pin confguration pin no. pin name description 1 out1 output, channel 1 2 -in1 negative input, channel 1 3 +in1 positive input, channel 1 4 +v s positive supply 5 +in2 positive input, channel 2 6 -in2 negative input, channel 2 7 out2 output, channel 2 8 out3 output, channel 3 9 -in3 negative input, channel 3 10 +in3 positive input, channel 3 11 -v s negative supply 12 +in4 positive input, channel 4 13 -in4 negative input, channel 4 14 out4 output, channel 4 clc1011 pin confguration clc2011 pin confguration 2 3 5 4 +in +v s -in 1 -v s out - + 2 3 4 5 6 7 8 out2 +in1 -in2 +in2 1 -in1 out1 -v s +v s clc4011 pin confguration 2 3 4 11 12 13 14 -in4 +in1 out4 +in4 1 -in1 out1 5 6 7 out2 -in2 +in2 8 9 10 +in3 -in3 out3 +vs -vs
data sheet c omlinear clc1011, clc2011, clc4011 low power, low cost, rail-to-rail i/o amplifers rev 1a ?2009 cadeka microcircuits llc www.cadeka.com 3 absolute maximum ratings the safety of the device is not guaranteed when it is operated above the absolute maximum ratings. the device should not be operated at these absolute limits. adhere to the recommended operating conditions for proper de - vice function. the information contained in the electrical characteristics tables and typical performance plots refect the operating conditions noted on the tables and plots. parameter min max unit supply voltage 0 6 v input voltage range -v s -0.5v +v s +0.5v v continuous output current -40 40 ma reliability information parameter min typ max unit junction temperature 175 c storage temperature range -65 150 c lead temperature (soldering, 10s) 260 c package thermal resistance 5-lead sc70 tbd c/w 5-lead sot23 221 c/w 6-lead sot23 177 c/w 8-lead soic 100 c/w 8-lead msop 139 c/w 14-lead tssop tbd c/w notes: package thermal resistance ( q ja ), jdec standard, multi-layer test boards, still air. esd protection product sc70-5 sot23-5 soic-8 msop-8 soic-14 tssop-14 human body model (hbm) tbd tbd 2kv tbd tbd tbd charged device model (cdm) tbd tbd 2kv tbd tbd tbd recommended operating conditions parameter min typ max unit operating temperature range -40 +85 c supply voltage range 2.5 5.5 v
data sheet c omlinear clc1011, clc2011, clc4011 low power, low cost, rail-to-rail i/o amplifers rev 1a ?2009 cadeka microcircuits llc www.cadeka.com 4 electrical characteristics at +2.7v t a = 25c, v s = +2.7v, r f = r g =5k, r l = 10k to v s /2, g = 2; unless otherwise noted. symbol parameter conditions min typ max units frequency domain response ugbw ss unity gain -3db bandwidth g = +1, v out = 0.02v pp 4.9 mhz bw ss -3db bandwidth g = +2, v out = 0.2v pp 3.2 mhz bw ls large signal bandwidth g = +2, v out = 2v pp 1.4 mhz gbwp gain bandwdith product g = +11, v out = 0.2v pp 2.5 mhz time domain response t r , t f rise and fall time v out = 1v step; (10% to 90%) 163 ns t s settling time to 0.1% v out = 1v step 500 ns os overshoot v out = 1v step <1 % sr slew rate 1v step 5.3 v/s distortion/noise response hd2 2nd harmonic distortion v out = 1v pp , 10khz -72 dbc hd3 3rd harmonic distortion v out = 1v pp , 10khz -72 dbc thd total harmonic distortion v out = 1v pp , 10khz 0.03 % e n input voltage noise > 10khz 21 nv/hz x talk crosstalk channel to channel, v out = 2v pp , 10khz 82 db channel to channel, v out = 2v pp , 50khz 74 db dc performance v io input offset voltage 0.5 mv dv io average drift 5 v/c i b input bias current 90 na di b average drift 32 pa/c psrr power supply rejection ratio (1) dc 55 83 db a ol open-loop gain v out = v s / 2 90 db i s supply current per channel 136 a input characteristics r in input resistance non-inverting 12 m c in input capacitance 2 pf cmir common mode input range -0.25 to 2.95 v cmrr common mode rejection ratio dc 81 db output characteristics v out output voltage swing r l = 10k to v s / 2 0.02 to 2.68 v r l = 1k to v s / 2 0.05 to 2.63 v r l = 200 to v s / 2 0.11 to 2.52 v i out output current 30 ma notes: 1. 100% tested at 25c
data sheet c omlinear clc1011, clc2011, clc4011 low power, low cost, rail-to-rail i/o amplifers rev 1a ?2009 cadeka microcircuits llc www.cadeka.com 5 electrical characteristics at +5v t a = 25c, v s = +5v, r f = r g =5k, r l = 10k to v s /2, g = 2; unless otherwise noted. symbol parameter conditions min typ max units frequency domain response ugbw ss unity gain -3db bandwidth g = +1, v out = 0.02v pp 4.3 mhz bw ss -3db bandwidth g = +2, v out = 0.2v pp 3.0 mhz bw ls large signal bandwidth g = +2, v out = 2v pp 2.3 mhz gbwp gain bandwdith product g = +11, v out = 0.2v pp 2.5 mhz time domain response t r , t f rise and fall time v out = 1v step; (10% to 90%) 110 ns t s settling time to 0.1% v out = 2v step 470 ns os overshoot v out = 1v step <1 % sr slew rate 2v step 9 v/s distortion/noise response hd2 2nd harmonic distortion v out = 1v pp , 10khz -73 dbc hd3 3rd harmonic distortion v out = 1v pp , 10khz -75 dbc thd total harmonic distortion v out = 1v pp , 10khz 0.03 % e n input voltage noise > 10khz 22 nv/hz x talk crosstalk channel to channel, v out = 2v pp , 10khz 82 db channel to channel, v out = 2v pp , 50khz 74 db dc performance v io input offset voltage (1) -8 1.5 8 mv dv io average drift 15 v/c i b input bias current (1) 90 450 na di b average drift 40 pa/c psrr power supply rejection ratio (1) dc 55 85 db a ol open-loop gain v out = v s / 2 80 db i s supply current (1) per channel 160 235 a input characteristics r in input resistance non-inverting 12 m c in input capacitance 2 pf cmir common mode input range -0.25 to 5.25 v cmrr common mode rejection ratio (1) dc 58 80 db output characteristics v out output voltage swing r l = 10k to v s / 2 (1) 0.08 to 4.92 0.04 to 4.96 v r l = 1k to v s / 2 0.07 to 4.9 v r l = 200 to v s / 2 0.14 to 4.67 v i out output current 35 ma notes: 1. 100% tested at 25c
data sheet c omlinear clc1011, clc2011, clc4011 low power, low cost, rail-to-rail i/o amplifers rev 1a ?2009 cadeka microcircuits llc www.cadeka.com 6 typical performance characteristics t a = 25c, v s = +2.7v, r f = r g =5k, r l = 10k to v s /2, g = 2; unless otherwise noted. frequency response vs. c l frequency response vs. r l non-inverting frequency response inverting frequency response non-inverting frequency response at v s = 5v inverting frequency response at v s = 5v normalize d magnitud e (1db/div) frequency (mhz) 0.01 0.1 r f = 5k? 1 10 g = 5 r f = 5k? g = 1 r f = 0 g = 2 r f = 5k? v o = 0.2v pp normalize d magnitud e (1db/div) frequency (mhz) 0.01 0.1 r f = 5k? 1 10 r f = 5k? r f = 5k? r f = 5k? v o = 0.2v pp normalize d magnitud e (1db/div) frequency (mhz) 0.01 0.1 r f = 5k? 1 10 g = 5 r f = 5k? g = 1 r f = 0 g = 2 r f = 5k? v o = 0.2v pp normalize d magnitud e (1db/div) frequency (mhz) 0.01 0.1 g = -10 1 10 g = -5 g = -1 g = -2 r f = 5k? magnitud e (1db/div) frequency (mhz) 0.01 0.1 1 10 c l r s = 100? c l r s = 0? c l r s = 0? c l r s = 0? 5k? 5k? r s c l r l v o = 0.05v + - magnitude (1db/div) frequency (mhz) 0.01 0.1 1 10 r l = 1k r l = 50 r l = 10k r l = 200
data sheet c omlinear clc1011, clc2011, clc4011 low power, low cost, rail-to-rail i/o amplifers rev 1a ?2009 cadeka microcircuits llc www.cadeka.com 7 typical performance characteristics t a = 25c, v s = +2.7v, r f = r g =5k, r l = 10k to v s /2, g = 2; unless otherwise noted. 2nd & 3rd harmonic distortion input voltage noise 2nd harmonic distortion vs. v out 3rd harmonic distortion vs. v out frequency response vs. v out open loop gain & phase vs. frequency magnitud e (1db/div) frequency (mhz) 0.01 0.1 1 10 v o = 4v pp v s = 5v v o = 1v pp v o = 2v pp ope n loo p gain (db) frequency (hz) 10 0 10 1 10 2 10 3 10 4 10 5 10 6 10 7 10 8 -20 60 140 no load 0 ope n loop phase (deg) -180 -90 0 -135 -45 no load r l = 10k? r l = 10k? v s = 5v 20 40 80 120 100 distortio n (dbc) output amplitude (v pp ) 0.5 1 1.5 2 100khz 50khz 10khz 2.5 -90 -80 -70 -60 -50 -40 -30 -20 10khz, 20khz 50khz distortio n (dbc) output amplitude (v pp ) 0.5 1 1.5 2 100khz 50khz 10khz 2.5 -90 -80 -70 -60 -50 -40 -30 -20 20khz distortio n (dbc) frequency (khz) 0 20 40 6 0 80 r l = 1k? 100 r l = 200? r l = 10k? r l = 1k? -90 -80 -70 -60 -50 -40 -30 -20 v o = 1v pp r l = 10k? r l = 200? nv/ hz frequency (hz) 0.1k 100k 10k 1k 1m 0 10 15 20 25 55 30 35 40 45 50 5
data sheet c omlinear clc1011, clc2011, clc4011 low power, low cost, rail-to-rail i/o amplifers rev 1a ?2009 cadeka microcircuits llc www.cadeka.com 8 typical performance characteristics - continued t a = 25c, v s = 5v, r f = r g =150, r l = 150, g = 2; unless otherwise noted. output swing vs. load pulse response vs. common mode voltage cmrr psrr cmr r (db) frequency (hz) 10 100 10000 1000 100000 -90 -80 -70 -60 0 -50 -40 -10 -30 -20 psrr (db) frequency (hz) 10 10000 1000 100 100000 -90 -70 -60 -50 -40 0 -30 -20 -10 -80 outpu t voltag e (0.27v/div) input voltage (0.4v/div) -2.0 0 2.0 -1.35 0 1.35 r l = 10k? r l = 1k? r l = 75/100? r l = 200? r l = 100? r l = 75? outpu t voltag e (0.5v/div) time (1 s/div) 1.2v offset 0.6v offset no offset -0.6v offset -1.2v offset crosstalk vs. frequency - 100 - 95 - 90 - 85 - 80 - 75 - 70 - 65 - 60 - 55 1 10 100 1,000 crosstalk (db) frequency (khz)
data sheet c omlinear clc1011, clc2011, clc4011 low power, low cost, rail-to-rail i/o amplifers rev 1a ?2009 cadeka microcircuits llc www.cadeka.com 9 application information general description the clcx011 family of amplifers are single supply, general purpose, voltage-feedback amplifers. they are fabricated on a complimentary bipolar process, feature a rail-to-rail input and output, and are unity gain stable. basic operation figures 1, 2, and 3 illustrate typical circuit confgurations for non-inverting, inverting, and unity gain topologies for dual supply applications. they show the recommended bypass capacitor values and overall closed loop gain equations. figure 4 shows the typical non-inverting gain circuit for single supply applicaitons. + - r f 0.1f 6.8f output g = 1 + ( r f /r g ) input +v s -v s r g 0.1f 6.8f r l figure 1. typical non-inverting gain circuit + - r f 0.1f 6.8f output g = - ( r f /r g ) for optimum input offset voltage set r 1 = r f || r g input +v s -v s 0.1f 6.8f r l r g r 1 figure 2. typical inverting gain circuit + - 0.1f 6.8f output g = 1 input +v s -v s 0.1f 6.8f r l figure 3. unity gain circuit + - r f 0.01f 6.8f out in +v s + r g figure 4. single supply non-inverting gain circuit power dissipation power dissipation should not be a factor when operating under the stated 10k ohm load condition. however, applications with low impedance, dc coupled loads should be analyzed to ensure that maximum allowed junction temperature is not exceeded. guidelines listed below can be used to verify that the particular application will not cause the device to operate beyond its intended operating range. maximum power levels are set by the absolute maximum junction rating of 150c. to calculate the junction temperature, the package thermal resistance value theta ja (? ja ) is used along with the total die power dissipation. t junction = t ambient + (? ja p d ) where t ambient is the temperature of the working environment.
data sheet c omlinear clc1011, clc2011, clc4011 low power, low cost, rail-to-rail i/o amplifers rev 1a ?2009 cadeka microcircuits llc www.cadeka.com 10 in order to determine p d , the power dissipated in the load needs to be subtracted from the total power delivered by the supplies. p d = p supply - p load supply power is calculated by the standard power equation. p supply = v supply i rms supply v supply = v s+ - v s- power delivered to a purely resistive load is: p load = ((v load ) rms 2 )/rload eff the effective load resistor (rload eff ) will need to include the effect of the feedback network. for instance, rload eff in fgure 3 would be calculated as: r l || (r f + r g ) these measurements are basic and are relatively easy to perform with standard lab equipment. for design purposes however, prior knowledge of actual signal levels and load impedance is needed to determine the dissipated power. here, p d can be found from p d = p quiescent + p dynamic - p load quiescent power can be derived from the specifed i s values along with known supply voltage, v supply . load power can be calculated as above with the desired signal amplitudes using: (v load ) rms = v peak / 2 ( i load ) rms = ( v load ) rms / rload eff the dynamic power is focused primarily within the output stage driving the load. this value can be calculated as: p dynamic = (v s+ - v load ) rms ( i load ) rms assuming the load is referenced in the middle of the power rails or v supply /2. figure 4 shows the maximum safe power dissipation in the package vs. the ambient temperature for the packages available. 0 0.5 1 1.5 2 - 40 - 20 0 20 40 60 80 maximum power dissipation (w) ambient temperature ( c) sot23 - 5 soic - 8 msop - 8 sot23 - 6 figure 4. maximum power derating input common mode voltage the common mode input range extends to 250mv below ground and to 250mv above vs, in single supply operation. exceeding these values will not cause phase reversal. however, if the input voltage exceeds the rails by more than 0.5v, the input esd devices will begin to conduct. the output will stay at the rail during this overdrive condition. if the absolute maximum input voltage (700mv beyond either rail) is exceeded, externally limit the input current to 5ma as shown in figure 5. output input 10k figure 5. circuit for input current protection driving capacitive loads increased phase delay at the output due to capacitive loading can cause ringing, peaking in the frequency response, and possible unstable behavior. use a series resistance, r s , between the amplifer and the load to help improve stability and settling performance. refer to figure 6.
data sheet c omlinear clc1011, clc2011, clc4011 low power, low cost, rail-to-rail i/o amplifers rev 1a ?2009 cadeka microcircuits llc www.cadeka.com 11 + - r f input output r g r s c l r l figure 6. addition of r s for driving capacitive loads table 1 provides the recommended r s for various capacitive loads. the recommended r s values result in approximately <1db peaking in the frequency response. the frequency response vs. c l plot, on page 6, illustrates the response of the clcx011. c l (pf) r s () -3db bw (khz) 10pf 0 2.2 20pf 0 2.4 50pf 0 2.5 100pf 100 2 table 1: recommended r s vs. c l for a given load capacitance, adjust r s to optimize the tradeoff between settling time and bandwidth. in general, reducing r s will increase bandwidth at the expense of additional overshoot and ringing. overdrive recovery an overdrive condition is defned as the point when either one of the inputs or the output exceed their specifed voltage range. overdrive recovery is the time needed for the amplifer to return to its normal or linear operating point. the recovery time varies, based on whether the input or output is overdriven and by how much the range is exceeded. the clcx011 will typically recover in less than 50ns from an overdrive condition. figure 7 shows the clc1011 in an overdriven condition. - 3 - 2.5 - 2 - 1.5 - 1 - 0.5 0 0.5 1 1.5 2 2.5 3 0 2 4 6 8 10 12 14 16 18 20 input/output voltage (v) time (us) output input g = 5 figure 7. overdrive recovery layout considerations general layout and supply bypassing play major roles in high frequency performance. c adeka has evaluation boards to use as a guide for high frequency layout and as an aid in device testing and characterization. follow the steps below as a basis for high frequency layout: ? include 6.8f and 0.1f ceramic capacitors for power supply decoupling ? place the 6.8f capacitor within 0.75 inches of the power pin ? place the 0.1f capacitor within 0.1 inches of the power pin ? remove the ground plane under and around the part, especially near the input and output pins to reduce parasitic capacitance ? minimize all trace lengths to reduce series inductances refer to the evaluation board layouts below for more information. evaluation board information the following evaluation boards are available to aid in the testing and layout of these devices: evaluation board # products ceb011 clc1011 in sc70 ceb002 clc1011 in sot23 ceb006 clc2011 in soic ceb010 clc2011 in msop ceb018 clc4011 in soic ceb017 clc4011 in tssop
data sheet c omlinear clc1011, clc2011, clc4011 low power, low cost, rail-to-rail i/o amplifers rev 1a ?2009 cadeka microcircuits llc www.cadeka.com 12 evaluation board schematics evaluation board schematics and layouts are shown in figures 8-14. these evaluation boards are built for dual- supply operation. follow these steps to use the board in a single-supply application: 1. short -vs to ground. 2. use c3 and c4, if the -v s pin of the amplifer is not directly connected to the ground plane. figure 8. ceb002 & ceb011 schematic figure 9. ceb002 top view figure 10. ceb002 bottom view figure 11. ceb011 top view figure 12. ceb011 bottom view
data sheet c omlinear clc1011, clc2011, clc4011 low power, low cost, rail-to-rail i/o amplifers rev 1a ?2009 cadeka microcircuits llc www.cadeka.com 13 figure 13. ceb006 & ceb010 schematic figure 14. ceb006 top view figure 15. ceb006 bottom view figure 16. ceb010 top view figure 17. ceb010 bottom view
data sheet c omlinear clc1011, clc2011, clc4011 low power, low cost, rail-to-rail i/o amplifers rev 1a ?2009 cadeka microcircuits llc www.cadeka.com 14 figure 18. ceb018 & ceb017 schematic figure 19. ceb018 top view figure 20. ceb018 bottom view
data sheet c omlinear clc1011, clc2011, clc4011 low power, low cost, rail-to-rail i/o amplifers rev 1a ?2009 cadeka microcircuits llc www.cadeka.com 15 mechanical dimensions sot23-5 package sot23-6
data sheet c omlinear clc1011, clc2011, clc4011 low power, low cost, rail-to-rail i/o amplifers rev 1a ?2009 cadeka microcircuits llc www.cadeka.com 16 mechanical dimensions continued soic-8 package msop-8 package 3.0 3.0 3.0 e 2 3 4 5 6 7 dimension "e1" and "e2" does not include inter lead flash or protr usion. e s e/2 2x ccc a b c e b e 2 3 7 2 6 4 d2 a2 a a1 e a e e c e bbb a b c m 4 3 aaa a e1 e2 e1 e detail a a a section a - a b c c1 b1 scale 40:1 t1 t2 plane 0.25mm r1 r l l1 03 02 01 e h e e3 e4 1 2 b d 5 symbol min max
for additional information regarding our products, please visit cadeka at: cadeka.com cadeka, the cadeka logo design, comlinear, the comlinear logo design, and arctic are trademarks or registered trademarks of cadeka microcircuits llc. all other brand and product names may be trademarks of their respective companies. cadeka reserves the right to make changes to any products and services herein at any time without notice. cadeka does not assume any responsibility or liability arising out of the application or use of any product or service described herein, except as expressly agreed to in writing by cadeka; nor does the purchase, lease, or use of a product or service from cadeka convey a license under any patent rights, copyrights, trademark rights, or any other of the intellectual property rights of cadeka or of third parties. copyright ?2009 by cadeka microcircuits llc. all rights reserved. cadeka headquarters loveland, colorado t: 970.663.5452 t: 877.663.5452 (toll free) data sheet c omlinear clc1011, clc2011, clc4011 low power, low cost, rail-to-rail i/o amplifers rev 1a mechanical dimensions continued soic-14 package sc70-5 package symbol min max e b e d c l he c l c l a a2 a1 e c c l l q1 a m p l i f y t h e h u m a n e x p e r i e n c e

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